1. Field of Invention
The present invention relates to a method of manufacturing bumps. More particularly, the present invention relates to a process of fabricating bumps having a shorter contact period with etchant so that volume reduction of the bumps is minimized.
2. Description of Related Art
In this information explosion age, electronic products are used almost everywhere. Computer and processing stations driven by powerful integrated circuits are employed in offices, educational institutions, recreational industries, business and commercial companies. As electronic technology continues to progress, products having more powerful functions and more attuned to personal needs are developed. Furthermore, most electronic products are increasingly light and compact thanks to the efficient fabrication of many types of high-density semiconductor packages. A major innovation is the flip chip design capable of cramming of a considerable number of integrated circuits together. In a flip-chip design, a plurality of bumps is formed on the bonding pads of a silicon chip. Each bump directly contacts a corresponding contact point on a substrate so that the chip and the substrate are electrically connected. Compared with the conventional wire-bonding and tape automated bonding (TAB) method of joining a chip with a substrate, the flip-chip design has a shorter overall conductive path and hence a better electrical connectivity. In addition, the backside of the chip may be exposed to facilitate heat dissipation during operation. Due to the distinguishing advantages of flip-chip packages, semiconductor manufacturing favors its production.
FIGS. 1 to 7 are partially magnified cross-sectional views of structures on the surface of a silicon wafer showing the progression of steps for producing bumps on the wafer according to a conventional method. As shown in FIG. 1, a silicon wafer 110 is provided. The wafer 110 has an active surface 112. The wafer 110 further includes a passivation layer 114 and a plurality of bonding pads 116 (only one of them is shown) on the active surface 112 of the wafer 110. The passivation layer 114 exposes the bonding pad 116.
As shown in FIG. 2, an adhesion layer 120 is formed over the active surface 112 of the wafer 110 by conducting a sputtering operation. The adhesion layer 120 covers the bonding pad 116 and the passivation layer 114. Thereafter, a barrier layer 130 is formed over the adhesion layer 120 by conducting a sputtering or an electroplating operation. A wettable layer 140 is formed over the barrier layer 130 by conducting a sputtering or an electroplating operation. Here, the fabrication of a so-called under-bump metallic layer 142 is complete. The under-bump metallic layer 142 actually is a composite layer comprising the adhesion layer 120, the barrier layer 130 and the wettable layer 140.
As shown in FIG. 3, a photolithographic operation is conducted by forming a photoresist layer 150 over the wettable layer 140, exposing the photoresist layer 150 to light and then developing the photoresist layer. Ultimately, a pattern (not shown) is transferred to the photoresist layer 150. The photoresist layer 150 now contains a plurality of openings 152 (only one is shown) that expose the wettable layer 140 above the bonding pad 116.
As shown in FIG. 4, metal is deposited to refill the opening by conducting an electroplating operation so that a plurality of solder bumps 160 (only one is shown) is formed inside the opening 152 of the photoresist layer 150. The solder bump 160 completely covers the exposed wettable layer 140.
As shown in FIGS. 4 and 5, the photoresist layer 150 is completely removed from the top of the wettable layer 140.
As shown in FIGS. 5 and 6, the under-bump metallic layer 142 outside the solder bump 160 region is removed by etching. Consequently, only the residual under-bump metallic layer 142 remains underneath the solder bump 160. The passivation layer 114 above the wafer 110 is now exposed.
As shown in FIG. 7, a reflow operation is conducted by sprinkling flux over the wafer 100 and heating to a temperature such that the solder bump 160 starts to melt and turns into a hemispherical shape bump 170. The bump 170 is actually a composite structure that includes the under-bump metallic layer 142 and the solder bump 160.
In the fabrication process as shown in FIGS. 1 to 7, etchant is used to remove the wettable layer 140, the barrier layer 130 and the adhesion layer 120 in sequence (not shown), that is, the under-bump metallic layer 142. During the etching of wettable layer 140, the barrier layer 130 or the adhesion layer 120, the etchant may come in contact with the solder bump 160 and etch away a portion of the solder bump 160 layer. Hence, overall thickness of the solder bump 160 may be reduced leading to material wastage and difficulty in controlling solder bump 160 quality.
FIGS. 8 and 9 are schematic cross-sectional views of bumps on a silicon wafer fabricated according to another conventional method. As shown in FIG. 8, a photoresist layer 250 is formed over an under-bump metallic layer 242 after a photolithographic process. The photoresist layer 250 has a plurality of openings 252 (only one is shown) that exposes the under-bump metallic layer 242 above a bonding pad 216. An electroplating operation is conducted to fill the openings 252 and form a first solder bump 260. The solder bump is made from copper, for example. A second electroplating operation is carried out to form a second solder bump 262 over the first solder bump 260. The second solder bump 262 extends over the photoresist layer 250. The second solder bump 262 is made from lead-tin alloy, for example. The photoresist layer 250 is removed as shown in FIG. 9. Thereafter, a reflow operation is conducted by sprinkling flux over the wafer and heating the wafer to melt the second solder bump 262 partially and enclose the first solder bump 260. In addition, the second solder bump 262 runs down over the under-bump metallic layer 242 and forms a blob of material having a hemispherical structure. Finally, the exposed under-bump metallic layer 242 is removed so that only the under-bump metallic layer 242 underneath the first solder bump 260 and the second solder bump 262 remains. However, during the etching of the under-bump metallic layer 242, etchant (not shown) will contact the second solder bump 262. Hence, a portion of the second solder bump 262 is removed and volume of the second solder bump 262 is reduced leading to material wasting and difficulty in controlling the ultimate dimension of the second solder bump 262.